Field
Aspects of the present disclosure relate generally to measuring load current, and more particularly, to an apparatus and method for measuring load current by applying a compensated gain to a voltage derived from a drain-to-source voltage of one or more power gating devices.
Background
Current supplied to one or more cores of an integrated circuit (IC) is typically gated through a power gating circuit. A power gating circuit typically comprises one or more power gating devices (e.g., PMOS devices) (also referred to as block head switches (BHS)) connected in parallel between a voltage rail (Vdd) and one or more cores of the IC. To selectively supply power to the one or more cores, the gate voltage of the PMOS device may be set to approximately zero (0) Volts to turn on the device and allow current to flow to the one or more cores, and the gate voltage may be set to approximately Vdd to turn off the device, and prevent current from flowing to the one or more cores.
In many applications, the current supplied to the one or more cores (the “load current”) may be measured and controlled so that the IC may be operated safely and/or for other purposes. One way of measuring the load current is to sense the drain-to-source voltage (Vds) across the one or more parallel PMOS devices. Assuming that the drain-to-source resistance (Rds) of the one or more PMOS devices is constant, the sensing of Vds provides an indication of the load current.
However, the Rds of the one or more PMOS devices varies with temperature and with the gate-to-source voltage (Vgs). The Vgs may vary due to intentional variation of Vdd for different applications. Because Rds varies with temperature and Vgs, simply sensing Vds of the one or more PMOS devices to determine the load current produces errors in the current measurement.